EEE4120F

This is the first lecture for this course, mainly a Meet & Greet and explanation of how the course is structured and what is involved. Have a look though this lecture and then give Quiz0 a try..

Read L01: Asanovic et al., The landscape of parallel computing research: A view from Berkeley
Read L01b: Asanovic et al.,A view of the parallel computing landscape (recommended easier read)

Terms, Validation vs. Verification, Commonly used verification Amdahl’s Law, Dealing with reading assignments. Then discussion bridging to Prac1 and use of golden measure. Discuss reading R01.

 Lecture2(notes).pdf : lecture printed with in notes view.

Lecture 03
Considerations for EDGE computing & relevance of HPES to such system development.
- Microprocessor-based vs. FPGA-based solutions for reconfigurable computing
- Platform & tools we will use
- GPUs (issues and benefits) and programming of these

Reading tasks

• Reading R02 : What is edge computing by E. Hamilton
• Read ‘About’ page for Valgrind

Links (suggested further reading or activities):

• Octave Introduction
• Latex Stack Exchange
• Latex WikiBook

OpenCL Overview. How to program in OpenCL. You may want to hyperspace to slide 42 if you want to get going with Prac2 asap. (some clickable Voice annotations in the PowerPoint slides updated).
OpenCL example: OpenCL_mmexample.zip

Lecture 05
Performance benchmarking (Part 1). Basic wall-clock benchmarking techniques.

Code mentioned in the slides:
Cycle.h Cycles.c

Performance benchmarking (Part 2).
- Metrics of Performance.
- Average Cycles Per Instruction (ACPI)
- Cost vs. Performance
- SWAP
- Profiling code (Reading: Valgrind)

Links (suggested further reading or activities):

• Valgrind Quickstart

Parallel Computing Fundamentals. Large Scale Parallelism. Mainstream parallel. Classic Parallel approaches. Flynns Taxonomy. Some Calculations - effective parallelism, parallel Efficiency, Gustafson's Law.

L7_learning_activity_A.pdf: Considering if SPMD or MPMD better than SPSD
L7_learning_activity_B.pdf: Estimation for maximum effective parallelism

(Excel document that illustrates to the solution discussed in slides: L7-activity calc.xlsx)

Watch:

• (recommended): 9th Gen Intel CPU Comparison - i5 vs i7 vs i9 Benchmarks
• Watch (recommended): Intel to Make ARM RISC-V Chips! (manufacturing IP by RISC-V community)
• Watch (optional): Intel's Xeon Phi (an unusual accelerator compared to GPUs)
• Watch (optional): AMD Ryzen 9 5950X vs Intel i9-10900K CPU Comparison (the procedure for benchmarking explained is useful but takes a whole to explain).
• Watch (optional): Everything you need to know about Intel's 11th generation
• Watch (if haven't already): Understanding Parallel Computing (Part 2): The Lawn Mower Law

Amdahl's Law for the Multicore Era and Base Core Equivalents (BCE).

Reading: Hill and Marty 2008: "Amdahl's Law in the Multicore Era" source: https://ieeexplore.ieee.org/abstract/document/4563876

Steps in parallelizing programs. Understand the problem. Partitioning. Granularity. Identify data dependencies. In these presentation covering steps 1-3: 1) Understand the problem, 2) Partitioning (i.e. separation into main tasks), 3) Granularity (assessing granularity of the problem vs. the parallelism).

Continuing the steps of designing parallel systems. Covering Steps 5-7: 5) Synchronization, 6) Load balancing, 7) Performance analysis and tuning. (Step 4 is a rather elaborate step, involving communication and integration of subsystems and is therefore covered in a lecture on its own).

Step 4: communication: Factors related to Communication; Cost of communications; Latency vs. Bandwidth; Baud rate vs. Bandwidth; Effective bandwidth; Visibility of Communications; Synchronous vs. asynchronous; Scope of communications; Collective communications; Efficiency of communications.
Class Activity 1 (Effective Bandwidth)

Distributed and Shared Memory Architectures: Distributed memory infrastructure; Shared memory infrastructure; Hybrid memory infrastructure; Warming up for MMU, DMA and memory considerations (to be delved into next term).

Your Own Digital Accelerator (YODA) Project; Discussion of Digital Accelerators.
(if annotations not working in pptx, try this mp4 version)

Programmable Logics and FPGAs Interns. Topics covered:

• Programmable Logic Devices
• What is so special about FPGAs
• FPGA interns
• Xilinx Slices {know what a slice is conceptually, no details or specifics need be know for tests}.

• Deepak Tala’s "Verilog Tutorial"
• Explore Verilog resources and examples at www.asic-world.com/verilog

Coding in Verilog: Basics of Verilog coding. Exercise in Verilog. Verilog simulators. Intro to Verilog in Vivado/ISE. Test bench. Generating Verilog from Schematic Editors. (This presentation does recap various aspects covered in EEE3096S ES-II).

Watch:

• Xilinx Vivado - Installation (by K. Crankshaw)
• Xilinx Vivado - Simulation (by K. Crankshaw)
• Simulation using iSim in Xilinx Vivado (by T. Briggs)

Recommended: give EDA playground (www.edaplayground.com) a try, you may want to set up your own login for using the tool. Take a look at the useful tutorial and support that is available on ASIC World at www.asic-world.com/examples/verilog.

Topics include: Brief recap (of Verilog items from lect 15); Busses and Endianness; Functions in Verilog; Implementing state machines;
The zip file contains the code for AliveFSM mentioned in the slides and the 'CosmicDetector' C starting point for the voluntary learning activity described at end of lecture.
AliveFSM and activity (statemachine example and more involved CosmicDetector class activity)

Blocking and non-blocking simulation example.

Topics covered: Attributes; Constraints; UCF Files; Xilinx Design Constraints

{many of these slides won't be examinable, slides relevant to exams: 4-7, don't need to know syntax for UCF (skip 8-13), be familar with what XDC is but won't be expected to know use this tool and don't need to worry with the UCF tutorial, although useful to try it if you plan to use a Xilinx FPGA board.}

FPGA and CPU Performance Comparison (audio annotations in pptx).
Topics covered: FPGA performance evaluation; FPGA vs CPU performance; FPGA families; YODA issues (not examined).
Class Activity (manually place and route a bitfile)
Class Activity Solution

HDL Imitation method. Using standard benchmarks for FPGAs. Amdahl's Law for FPGAs.

The 'HDL Imitation' method is a suggested approach to quickly get together both a golden measure and a start on a HDL solution. Various case studies are used in these slides for examples of how the methods are applied.

Tips on strategizing your YODA projects, and deciding roles for the team members. Plans on marking and review of MS1 submission and onward to MS2 and expectations for that milestone.

More Verilog; Configuration Architectures; RC Building Blocks (for IP Cores); Basic handshaking, latches and other interface ingredients.
This lecture provides theories to assist in how subsystems might cooperate in more robust and dependable ways.(Includes non-examined case studies of unusual FPGA platform designs). This might feel like 3 lectures in one... it effectively is, but has been streamlined and the exam syllabus will identify aspects of this lecture that should be focused on for preparing for the exam.
Example of handshaking in Verilog: GenResult
GenResults.v testbench: GenResults_tb.v

On-chip interconnection bus topologies; Interfacing standards; Memory types; Memory Control Unit (MCU) (Part 1 of 2); Using Memory and MCU in Verilog

Memory Control Units (part 2 of 2): Dual-port memory control unit, Setting up memory in code and in simulation; FIFO and LIFO. {optional reading: On-chip Interfacing Standards: Wishbone and how it works, The Altera/Intel Avalon Bus}.

HPES Development Process and Management Aspects: Where work is done; Division of Labour (DoL); HPES development process; Setting system objectives; Costs and risks; Monitoring progress; Documentation; Effort, Productivity and Progress. (Indeed, design and development team factors that university graduates working on advanced embedded systems should be aware of.)

(Optional extra slides re intro to Doxygen)

Note that slide 15 onward are optional reading and will not be examined this year.

Comments/study tips: '[Software] Quality Assurance'. NB: For the exam, you can skip most of this lecture, it is largely optional additional reading and will not be examined! However, as per my earlier comment, it is good for a university graduate to know about these issues. The '[software]' is in square brackets because, while much of these slides do related to software, much of the aspects also relate to HPES and FPGA-based HDL disign work.

Topics: What is quality?; Software quality; Software quality assurance (SQA); Software quality systems; Consequences of bad SQA; An evolutionary model of SQA in organizations; Kaizen of software and Formal Specifications as getting closer to accurately specifying quality.