Main Project Status (05/20/2016 - 03:17:32)
Project File: YODA-ASG.xise Parser Errors: No Errors
Module Name: Main Implementation State: Synthesized (Stopped)
Target Device: xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
 
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri May 20 03:17:22 2016000
Translation ReportOut of DateFri May 20 03:10:14 2016001 Info (0 new)
Map ReportOut of DateFri May 20 03:12:27 201601 Warning (0 new)10 Infos (0 new)
Place and Route ReportOut of DateFri May 20 03:13:42 2016012 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportOut of DateFri May 20 03:14:04 2016003 Infos (0 new)
Bitgen ReportOut of DateFri May 20 03:00:28 201601 Warning (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu May 19 22:57:10 2016
WebTalk ReportOut of DateFri May 20 03:00:29 2016
WebTalk Log FileOut of DateFri May 20 03:00:40 2016

Date Generated: 05/20/2016 - 03:17:37