Clock Project Status
Project File: YODAProjectCode.xise Parser Errors: No Errors
Module Name: Clock Implementation State: Programming File Generated
Target Device: xc7a100t-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 30 126,800 1%  
    Number used as Flip Flops 30      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 30 63,400 1%  
    Number used as logic 29 63,400 1%  
        Number using O6 output only 0      
        Number using O5 output only 28      
        Number using O5 and O6 1      
        Number used as ROM 0      
    Number used as Memory 0 19,000 0%  
    Number used exclusively as route-thrus 1      
        Number with same-slice register load 0      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 8 15,850 1%  
Number of LUT Flip Flop pairs used 30      
    Number with an unused Flip Flop 0 30 0%  
    Number with an unused LUT 0 30 0%  
    Number of fully used LUT-FF pairs 30 30 100%  
    Number of unique control sets 1      
    Number of slice register sites lost
        to control set restrictions
2 126,800 1%  
Number of bonded IOBs 13 210 6%  
    Number of LOCed IOBs 13 13 100%  
Number of RAMB36E1/FIFO36E1s 0 135 0%  
Number of RAMB18E1/FIFO18E1s 0 270 0%  
Number of BUFG/BUFGCTRLs 1 32 3%  
    Number used as BUFGs 1      
    Number used as BUFGCTRLs 0      
Number of IDELAYE2/IDELAYE2_FINEDELAYs 0 300 0%  
Number of ILOGICE2/ILOGICE3/ISERDESE2s 0 300 0%  
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0      
Number of OLOGICE2/OLOGICE3/OSERDESE2s 0 300 0%  
Number of PHASER_IN/PHASER_IN_PHYs 0 24 0%  
Number of PHASER_OUT/PHASER_OUT_PHYs 0 24 0%  
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 96 0%  
Number of BUFRs 0 24 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 240 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of IBUFDS_GTE2s 0 4 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 6 0%  
Number of IN_FIFOs 0 24 0%  
Number of MMCME2_ADVs 0 6 0%  
Number of OUT_FIFOs 0 24 0%  
Number of PCIE_2_1s 0 1 0%  
Number of PHASER_REFs 0 6 0%  
Number of PHY_CONTROLs 0 6 0%  
Number of PLLE2_ADVs 0 6 0%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Average Fanout of Non-Clock Nets 1.32      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue 19. Apr 10:52:59 2016000
Translation ReportCurrentTue 19. Apr 10:53:07 2016001 Info (0 new)
Map ReportCurrentTue 19. Apr 10:53:38 2016   
Place and Route ReportCurrentTue 19. Apr 10:54:11 2016000
Power Report     
Post-PAR Static Timing ReportCurrentTue 19. Apr 10:54:28 2016003 Infos (3 new)
Bitgen ReportCurrentTue 19. Apr 10:55:06 2016001 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateTue 19. Apr 10:55:07 2016
WebTalk Log FileOut of DateTue 19. Apr 11:36:39 2016

Date Generated: 04/19/2016 - 16:14:35