Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/VADER |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2016-04-18T11:02:00 |
PROP_intWbtProjectID=22AFF2A807014D8EAE29AF91DE797AA6 |
PROP_intWbtProjectIteration=137 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_selectedSimRootSourceNode_behav=work.VADER |
PROP_AutoTop=true |
PROP_DevFamily=Artix7 |
PROP_ibiswriterOutputFile=TopLevel |
PROP_DevDevice=xc7a100t |
PROP_DevFamilyPMName=artix7 |
PROP_DevPackage=csg324 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-3 |
PROP_PreferredLanguage=Verilog |
PROP_netgenPostMapSimModelName=TopLevel_map.v |
PROP_netgenPostParSimModelName=TopLevel_timesim.v |
PROP_netgenPostSynthesisSimModelName=TopLevel_synthesis.v |
PROP_netgenPostXlateSimModelName=TopLevel_translate.v |
FILE_UCF=1 |
FILE_VERILOG=6 |