Welcome to HPES!

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Objective of this Course

The objective of this course is to develop an understanding of the concepts involved in the design and development of high performance and special-purpose digital computing systems, in terms of both hardware and software design. The course builds on a basic understanding of parallel computing principles and embedded systems, expanding the students' expertise into the specialized fields of reconfigurable computing, heterogeneous computing and high performance parallel computing. Many of the topics covered in this course are relevant towards advanced computing skills related to Industry 4.0, particularly computing solutions for the processing and leveraging of data close to where the data is collected, which is a major advantage of high-performance computing situated on embedded platforms, which is a major focus of this course. But note that this course do not go into much details of data processing and algorithms for leveraging data; rather baseline technologies and tool understanding is taught in this course but you could built upon these techniques to develop the necessary application processing skills through other courses (e.g. a Machine Learning, or Pattern Recognition or Data Analytics courses that are offered by other departments at UCT or available as online courses). Coursework in this course involves laboratory assignments, a project and a conceptual assignment (which involves reading technical articles and completing a thinking and design exercise, these used in assessing ECSA Graduate Attribute 2, "Application of scientific and engineering knowledge"). A number of compulsory tests are held, for which advanced notice and a syllabus is provided. The lecture sessions include presentations by lecturers, seminars and workshops during which students learn fundamental theories, brainstorm ideas, and discuss influential and recent publications in the field.Students are required to bring their own laptops to the Thursday (practical work) sessions.

Course Information

SAQA Credits 16 Credits
Prerequisites EEE3096/5S
Lecture Times and Venues:
For this year, we're having a combination of lectures, pracs or some computer-based activities during lecture slots, as well as working through problems and occasional quizzes during the assigned lecture times. Attending class meetings is optional, but do try to attend quizzes and tests that are held in lectures, although the quizzes are schedule and announced ahead of time, and they are generally held at the start of the lecture (after which there may be occasionally be peer-marking and going over the quiz solutions). As will be explain in Lecture 1, you can apply for moving test marks (with the exception of the GA2 test) to the exam (e.g. if you will not be able to attend tests). This year, the course has a sequence of weekly 'Learning' tasks and objectives, some 'seminar style' sessions to discuss topics and theories, which are aimed to assist students in the assigned reading tasks. Graduate Attribute Outcome 2 (GA2) requirements are part of this course; there is a GA2 assignment, that includes reading tasks and problem-solving activities, involved for this. You need to satisfactorily complete the GA2 assignment and any related testing in order to receive DP for this course.
NOTE while attendance of classes is optional, students must plan their study to make sure that their learning is 'synched' with the various assessments involved (these assessments include assignment handends and tests). Tests and other assessments which will be announced in good time to assist you planning and time management.		 Weekly Routine:
Tuesday 16h00-18h00: Lecture Session; Assignment / Practical discussion. Seminar/Tools review. See announcement of 'Learning' plans and tasks for the week.
Wednesday 14h00-16h00: Possible venue can be booked if more course workspace needed.
Thursday 14h00-15h00: Prac, assignment/activity course work time. NB: bring your own laptop to the venue. Sometimes a quiz will be held during start of this period (tests and quizzes will be announced a week before).
Prac Times and Venues (tutor availability) Thu: 4pm - 6pm prac session
Pracs can be done on your own pc. Prac1 needs to be done individually, the other pracs can be done as a team of two. Plan with your team partner when to meet to work on pracs. Thursday session is an opportunity for tutor support. Prac times are otherwise flexible, Can work where you like.
DP Requirement Overall class average of 40%
Pass GA2 assignment and test.
Final Mark Weighting See course handout

preparatory Resources

For this course it is important that you have some C / C++ programming expertise. Have done some Hardware Description Language (HDL) coding (e.g. Verilog or VHDL would help - although in this course we will cover Verilog programming from a fairly basic level). You should understand computer hardware well, know some digital combinational logic, have a good understanding of digital circuits, have a basic understanding of pipeline and super-pipelined systems (although we will top up this understanding). Ideally you should have implemented a small HDL simulation (at least in terms of a schematic -> HDL generator). You should also have done software engineering, being comfortable with describing software designs, flow charts and state machines.

Some useful resources include, which can help you prepare for the course are:

Related Websites

For more information, refer to these websites: